library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder_32 is
    Port ( a : in  STD_LOGIC_VECTOR (31 downto 0);
           b : in  STD_LOGIC_VECTOR (31 downto 0);
           carryIn : in  STD_LOGIC;
           sum : out  STD_LOGIC_VECTOR (31 downto 0);
           carryOut : out  STD_LOGIC);
end adder_32;

architecture Behavioral of adder_32 is

	component adder_4 is
	    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
	           b : in  STD_LOGIC_VECTOR (3 downto 0);
	           carryIn : in  STD_LOGIC;
	           sum : out  STD_LOGIC_VECTOR (3 downto 0);
	           carryOut : out  STD_LOGIC);
	end component;

	signal sum_signal: std_logic_vector(31 downto 0):= X"00000000";
	signal c0: STD_LOGIC:='0';
	signal c1: STD_LOGIC:='0';
	signal c2: STD_LOGIC:='0';
	signal c3: STD_LOGIC:='0';
	signal c4: STD_LOGIC:='0';
	signal c5: STD_LOGIC:='0';
	signal c6: STD_LOGIC:='0';

begin

A0: adder_4 port map (a(3  downto 0 ), b(3  downto 0 ), carryIn, sum_signal(3 downto 0), c0);
A1: adder_4 port map (a(7  downto 4 ), b(7  downto 4 ), c0, sum_signal(7 downto 4), c1);
A2: adder_4 port map (a(11 downto 8 ), b(11 downto 8 ), c1, sum_signal(11 downto 8), c2);
A3: adder_4 port map (a(15 downto 12), b(15 downto 12), c2, sum_signal(15 downto 12), c3);
A4: adder_4 port map (a(19 downto 16), b(19 downto 16), c3, sum_signal(19 downto 16), c4);
A5: adder_4 port map (a(23 downto 20), b(23 downto 20), c4, sum_signal(23 downto 20), c5);
A6: adder_4 port map (a(27 downto 24), b(27 downto 24), c5, sum_signal(27 downto 24), c6);
A7: adder_4 port map (a(31 downto 28), b(31 downto 28), c6, sum_signal(31 downto 28), carryOut);
sum <= sum_signal;
end Behavioral;

